Field
The disclosed embodiments generally relate to techniques for improving performance in computer system processors. More specifically, the disclosed embodiments relate to the design of a processor, which reduces power consumption and improves die-area efficiency by combining a working register file and an architectural register into a single physical register file.
Related Art
In modern processor architectures, such as the SPARC™ processor architecture, the complete register state of a processor is often stored in a Working Register File (WRF) and an Architectural Register File (ARF). More specifically, the speculative register state of the processor is stored in the WRF, while its non-speculative register state is stored in the ARF. Instructions can read their source operands from either the WRF or the ARF, depending on which contains the latest version of the data. Instructions write destination operands to the WRF when they complete execution, and when the instructions ultimately commit, their result data is copied from the WRF to the ARF.
However, this WRF/ARF processor organization is not power-efficient because data needs to be copied between the WRF and the ARF, and this additional copying operation consumes power. It is also not area-efficient because, at any given time, many entries in the ARF are either unused or are storing data that will not be used by the processor. These entries correspond to the architectural registers that either have not been defined or are no longer live. Hence, the area used by such registers is essentially wasted.
Moreover, the WRF and ARF consume significant amounts of power and occupy a significant amount of semiconductor area because they contain many entries and provide multiple read and write ports. (In fact, the ARF for a recently developed SPARC™ processor contains approximately 1300 entries.)
Hence, it is desirable to be able to store the speculative and non-speculative register state for a processor without the above-described drawbacks of a WRF/ARF processor organization.